The present invention relates to a semiconductor integrated circuit and, particularly, to an A/D converter having a multiplying function in an encoder of a parallel comparison type A/D converter.
A digital signal process is intended for high performance, high integration and high function as a digital integrated circuit technique has been recently proceeded even in a field of a conventional signal process by an analog circuit. A/D converters are indispensable to digitally process an originally analog signal, such as a voice or an image.
FIG. 3 shows a conventional parallel comparison type A/D converter. Referring to FIG. 3, the A/D converter includes a reference voltage terminal 1, an analog input terminal 2, ladder resistors 3 connected in series between the reference voltage terminal 1 and a ground for determining the reference voltages of comparators 4, a plurality of comparators 4 aligned in parallel with each other, an encoder circuit 5, and digital output terminals 6 connected to the outputs of the encoder 5.
With such arrangement of the conventional A/D converter, a voltage applied to the reference voltage terminal 1 is divided by the plurality of ladder resistors 3 connected in series, and reference voltages thus divided from the voltage by the respective ladder resistors 3 are sequentially applied to first inputs of the plurality of comparators 4, respectively. The comparators 4 each compare the inputs of the reference voltages with the analog signal inputted to the analog input terminal 2 connected at their other inputs, and output the compared results. The outputs of the comparators 4 are coded by the encoder circuit 5, and digital data are outputted to the parallel output terminals 6 connected to the outputs of the encoder circuit 5. When the output includes N bits, (2.sup.N -1) comparators are required.
The conventional A/D converter will be described in more detail by referring to FIGS. 4 and 5. FIG. 4 shows a parallel comparison type A/D converter providing a 3-bit straight binary coded output, and FIGS. 5(a) and 5(b) show examples of the outputs of the comparators and the outputs of the encoder circuit of the A/D converter. Since the A/D converter uses parallel comparison, the outputs of the comparators 4 are all "1" (=high) or "0" (=low), or continuous two values having one different output, one of which indicates the value of the analog input. In the A/D converter of FIG. 4, the values example shown in the outputs are different bit outputs 4b and 4c.
When the encoder 5 is constructed as shown in FIG. 4 in the conventional A/D converter with the comparators 4 connected to the inputs of the encoder 5 as shown in FIG. 5(a), the output of the encoder 5 (6a is the most significant bit) produces "5" as shown in FIG. 5(b) with respect to the comparison output "5".
Since the conventional A/D converter is constructed as described above, a multiplier of another chip is required to produce a product of the digital output of the A/D converter and other data. Further, when a high speed multiplier is constructed, there arise drawbacks that the chip area of the multiplier of another chip is increased, and a number of multipliers must be integrated on the same chip.